Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one's-complement scheme instead of a two's-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better areaand energy-efficiency, compared to other multi-mode LDPC decoders. & 2015 Elsevier B.V. All rights reserved.